High-integration and high-performance LSIs have been realized by miniaturizing field effect transistors (hereinafter also referred to as FETs) that are the fundamental structural components of the LSIs, and achieving higher performance through the miniaturization. The performance of a FET is determined by how large the magnitude of the drive current is during ON-state operation and how small the magnitude of the channel leakage current is during OFF-state operation.
To reduce leakage currents, FD (Fully-Depleted) devices that have their channel regions completely depleted and have high resistances to short channel effects are expected as the next-generation fundamental structural components. Among those devices, multi-gate transistors are particularly attracting attention. Unlike a structure of a conventional single-gate type, a structure of a multi-gate type has a minute channel region surrounded by gate electrodes. Such a structure has the advantages that the potential controllability in the channel region is made higher, decreases of the potential barrier due to short-channeling of the device can be restrained, and the leakage current in the OFF state can be reduced.
What matters in the performance of an integrated circuit are the threshold value control in each device and an increase in drive current. In a fully-depleted device, the voltage at which inversion charges are generated is characteristically lower than that in a bulk-type device. Therefore, in a conventional polysilicon gate electrode having a work function as the bandgap end, the current in the OFF state (0 volt) becomes too large. As of today, examples of novel gate electrodes include a structure in which a metal is used as the gate electrode (a metal gate), and a structure in which a compound of a metal and a semiconductor (a silicide if the semiconductor is silicon) is used as the gate electrode (a silicide gate).
Since the drive current is the product of the carrier (charge carrier) density and the carrier mobility, increasing the motility is effective to increase the drive current. To increase the carrier mobility, there is a suggested method by which a compound of a metal and a semiconductor is used as the gate electrode, and strain is caused in the channel region through a volume change in the compound. This method is designed for Fin-FETs (so-called three-dimensional double-gate transistors). According to this method, to perform precise lithography on polysilicon covering a tall Fin-type channel region with a height of 50 to 100 nm, for example, a polysilicon film flattened by CMP is silicided. Therefore, in this method, the portion of the silicided gate electrode that is not located above the channel region has the same height as the portion of the silicided gate electrode located above the channel region.
Introduction of strain to the channel region of a tri-gate transistor or a nanowire transistor has also been tried without success.